CCD structures implemented in standard 0 . 18 m m CMOS technology

Introduction: Charge-coupled devices (CCDs) have conventionally used overlapping (0.5–2.5 mm) polysilicon gates to achieve charge transfer between gates with a very high charge transfer efficiency (CTE) [1]. Since conventional CMOS processes do not allow poly-overlaps, it was not possible to achieve a ‘true’ CCD structure in this process until now, though efforts were made in this direction [2]. With the aggressive scaling of CMOS technology to deep sub-micron dimensions, the design rules permit fabrication of polysilicon gates very close ( 0.24 mm) to each other. From device simulations, we find that this would allow the gate potentials to overlap, and create sufficient transverse field to transfer charges between adjacent gates. The size of the gap is critical and, from simulation studies, the minimum gap required for efficient charge transfer in 0.18 mm CMOS technology is found to be less than 0.4 mm. The actual gate gap used in our design was 0.24 mm, which ensures a smooth transfer of charges without potential ‘bumps’. Since medical applications require the use of very large pixels (30 30 mm) (both photodiodes as well as photo-gates), complete charge transfer is a major issue. If CCD structures could be implemented in current CMOS technologies, this problem can be circumvented. Photogate sensors suffer from lower sensitivity to lower wavelength photons (l , 450 nm) owing to absorption of these photons in the polysilicon layer (tpoly 150 nm). For specific applications where a scintillator layer converts the incoming radiation (ex. X-rays) to a particular wavelength in the visible spectrum (e.g. Gd2O2S:Tb; 545 nm) such problems can be eliminated. Moreover, since deep sub-micron technology is highly radiation tolerant, such pixels can be effectively used in applications involving harsh environments [3].